Research banner

Welcome to


Project 'Rathlin' aims to conduct research on developing programmable embedded platforms for remote and compute-intensive image processing applications.


Peer-reviewed papers in Journals and Conferences:


J3. D. Bhowmik, M. Oakes and C. Abhayaratne, Visual Attention-based Image Watermarking, IEEE Access, Dec. 2016. [DOI]

J2. M. Amiri, F. M. Siddiqui, C. Kelly, R. Woods, K. Rafferty & B. Bardak. FPGA-based soft-core processors for image processing applications, Journal of VLSI Signal Processing, 2016.

C10. R. Stewart, G. Michaelson, D. Bhowmik, P. Garcia and A. Wallace, A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs, International Workshop on Data Locality in Modern Computing Systems (DLMCS 2016), 14-16th Dec 2016, Granada, Spain.

C9. R. Stewart, An Image Processing Language: External and Shallow/Deep Embeddings, International workshop on Real World DSLs (RWDSL), Barcalona, Spain, March 12, 2016. [DOI]

C8. G. Michaelson, Are there Domain Specific Languages, International workshop on Real World DSLs (RWDSL), Barcalona, Spain, March 12, 2016. [DOI]

C7. C. Kelly, F.M Siddiqui, B. Bardak, Y. Wu, R. Woods and K. Rafferty, FPGA Soft-core Processors, Compiler and Hardware Optimisations validated using HOG, 12th International Symposium on Applied Reconfigurable Computing (ARC), Rio de Janeiro, March 22-24, 2016.


J1. R. Stewart, D. Bhowmik, A. Wallace and G. Michaelson, Profile Guided Dataflow Transformation for FPGAs & CPUs, Journal of Signal Processing Systems, Springer, 2015. [DOI][PDF]

C6. R. Stewart, D. Bhowmik, A. Wallace and G. Michaelson, RIPL: An Efficient Image Processing DSL for FPGAs, Workshop on FPGAs for Software Programmers, International Conference on Field-programmable Logic and Applications (FPL), London, UK September 2-4, 2015. [DOI]  

C5. R. Stewart, D. Bhowmik, G. Michaelson, S. B. Sholz and A. Wallace, Chaining the RIPL and SaC DSLs for Image Processing, 18th International Workshop on Compilers for Parallel Computing (CPC'15), London, UK, 7-9 January, 2015.


C4. B. Bardak, F.M Siddiqui, C. Kelly and R. Woods, Dataflow toolset for soft-core processors on FPGA for image processing applications, IEEE Conference on Signals, Systems and Computers, Asilomar, California, USA, November 2-5, 2014. [PDF]

C3. D. Bhowmik, R. Stewart, X. Qian, A. Wallace and G. Michaelson, Profile Driven Dataflow Optimisation of Mean Shift Visual Tracking, IEEE Global Conference on Signal and Information Processing (GlobalSIP), Atlanta, Georgia, USA, December 3-5, 2014. [Preprint] [DOI]

C2. F. M. Siddiqui, M. Russell, B. Bardak, R. Woods and K. Rafferty, IPPro: FPGA based Image Processing Processor, IEEE International Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, October 20-22, 2014. [PDF]

C1. C. Kelly, F. M. Siddiqui, B. Bardak and R. Woods, Histogram of Oriented Gradients front end processing: an FPGA Based Processor Approach, IEEE International Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, October 20-22, 2014. [PDF]

Technical reports:

T5. Rob Stewart, Fahad Siddiqui, Soft IPPro Report, Deliverable 7 (D7), Project Rathlin, July 2014. [PDF]

T4. Fahad Siddiqui, Architectural optimizations of IPPro to accelerate data-intensive image processing applications, Deliverable 5 (D5), Project Rathlin, August 2015. [PDF]

T3. Nathanael Baisa, Deepayan Bhowmik and Andrew Wallace, Behavioural analysis in public space: An integrated system model from individual tracking to crowd dynamics, Deliverable 11 (D11), Project Rathlin, August 2014. [PDF]

T2. Fahad Siddqui and Burak Bardak, Single-core Image Processing Processor (IPPro) architecture to accelerate image processing algorithms, Deliverable 4 (D4), Project Rathlin, May 2014. [PDF]

T1. Burak Bardak, Robert Stewart and Deepayan Bhowmik, Data-flow modeling to capture the processing and data organisation of image processing algorithms in language representation, Deliverable 1 (D1), Project Rathlin, February 2014. [PDF]

Workshop Presentations / Posters

W6. R. Stewart, D. Bhowmik, G. Michaelson, A. Wallace, P. Garcia, I. Ibrahim, High FPGAs for Image Processing, A DSL and program transformations. UK Manycore Conference (UKMAC), Edinburgh, UK, 10 May 2016. 

W5. A. M. Wallace, “Video Tracking using Profile Guided Dataflow Transformation”, presentation to UDRC Workshop on Hardware for Signal Processing Algorithms, Strathclyde, November 2015

W4. D. Bhowmik and A. Wallace, Counting people in crowd with visually salient low level features, Second Workshop, Visual Image Interpretation in Humans and Machines (ViiHM), Bath, UK, 1-2 July 2015. 

W3. A. M. Wallace, “Video Tracking using Profile Guided Dataflow Transformation”, presentation to Conference on Challenges in Dynamic Imaging Data, Isaac Newton Institute, Cambridge, June 2015.

W2. D. Bhowmik, J. Bouis, R. Stewart, A. Wallace and G. Michaelson, An FPGA-based Distributed Smart Camera Network, Workshop on the Architecture of Smart Cameras (WACS), Santiago de Compostela, Spain, 29-30 June 2015.

W1. R. Stewart and D. Bhowmik, Rathlin Image Processing Language (RIPL), Workshop on Real World Domain Specific Languages, Edinburgh, UK, 1st May 2014.

MSc Thesis:

M2. Matthew Russels, Acceleration of car sign detetction algorithm using the Zedbaord, MSc Project Report, Queens University, Belfast, UK, May 2014. [PDF

M1. Weihua Lin, Measuring Heart Rate using computer vision techniques on Android based mobile phones, MSc thesis, Heriot-Watt University, Edinburgh, UK, August 2014. [PDF