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Welcome to

Rathlin

Project 'Rathlin' aims to conduct research on developing programmable embedded platforms for remote and compute-intensive image processing applications.

Roger Woods

Professor

Email r.woods@qub.ac.uk 
roger
Website http://www.ecit.qub.ac.uk/Card/?name=r.woods
Phone

0044 - (0) 289 097 1892 / 4081

Contact

The Institute of Electronics, Communications and Information Technology (ECIT)
Queen’s University Belfast
NI Science Park
Queen’s Road
Queen’s Island
Belfast
BT3 9DT

Research interest

Implementation of complex programmable systems e.g. FPGA-based systems for signal processing and telecommunications including design flows, methodologies and applications.

Recent publications (Journals)

  • C. Zheng, X. Chu, J. McAllister and R. Woods, Real Fixed-Complexity Sphere Decoder for High Dimensional QAM-MIMO Systems, IEEE Trans. on Signal Proc., Vol. 59, No. 9, Sept. 2011, pp. 4493 - 4499.
  • W. Liu, L. Lu, M. O'Neill, E. E. Swartzlander Jr. and Roger Woods, Design of Quantum-dot Cellular Automata Circuits using Cut-Set Retiming, IEEE Trans. on Nanotechnology, Vol. 10, No 5, Sept 2011, pp. 1150 - 1160.
  • Q. Zhang, R. Woods and A. Marshall, Per-flow Queue Management Architectures for a Programmable Traffic Manager, IEEE Trans on VLSI Systems, 10.1109/TVLSI.2011.2162084, 15th August 2011.
  • R Veitch, L-M Aubert, R Woods and S Fischaber, FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition, Special issues on Selected Papers from the Southern Programmable Logic Conference (SPL2010), International Journal of Reconfigurable Computing, vol. 2011, Article ID 697080, 10 pages, 2011. doi:10.1155/2011/697080.
  • S O'Neill, R. Woods and A. Marshall, A Scalable and Programmable Modular Traffic Manager Architecture, ACM Transactions on Reconfigurable Technology and Systems, Vol. 4, Issue 2, June 2011.
  • S. McKeown and R. Woods, Low Power FPGA implementation of fast DSP algorithms: characterisation and manipulation of data locality, IET Proc. on Computer and Design Techniques, March 2011, Vol. 5, No. 2, pp. 136 - 144.
  • R. Woods, J Becker, P Athanas, F Morgan, Guest Editorial, ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2010.
  • B. McAllister, A. Marshall and R. Woods, A Programmable Architecture for Layered Multimedia Streams in IPv6 Networks, Special Issue on Recent Advances in Network and Parallel Computing, Journal of Networks, Vol. 5, No 1, 2010, pp. 65-74.
  • S Fischaber, R Woods and J McAllister, SoC Memory Hierarchy Derivation from Dataflow Graphs, (invited paper), Special issue on Sips2007, Journal of VLSI Signal Processing, Vol. 60, No. 3, 2010, pp345-361.
  • K. Compton, R. Woods, C. Bouganis and P Diniz, Guest Editorial,  ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol. 2, No. 4, Sept. 2009.
  • J. Bëcker, M. Hübner, R. Woods, P. Leong, R. Esser and L. Torres, Guest Editorial: Current Trends on Reconfigurable Computing, International Journal of Reconfigurable Computing, Hindawi Publishing Corp., Vol. 2008, 15 Dec. 2008.
  • R. F. Woods, J. V. McCanny and J. G. McWhirter, From Bit Level Systolic Arrays to HDTV Processor Chips (invited paper), Special issue on 20 years of ASAP, Journal of VLSI Signal Processing, Springer, ISSN:1939-8018, Vol. 53, No. 1-2, Nov. 2008, pp. 35 - 49.
  • Motuk, E., Woods, R., Bilbao, S. and McAllister, J., Design Methodology for Real-Time FPGA-Based Sound Synthesis, IEEE Trans. Signal Processing, vol. 55, no.12, Dec. 2007, pp. 5833-5845.
  • J. McAllister, R. Woods, S. Fischaber and E. Malins, Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Heterogeneous Platforms(invited paper), Special issue on Samos05, Journal of Systems Architecture, Elsevier Inc., North-Holland, Vol. 53 , No. 8, Aug. 2007, pp. 511-523.
  • E. F. Deprettre, R Woods, I Verbauwhede, Erwin de Kock, Transforming Signal Processing Applications into Parallel Implementations, EURASIP Journal on Advances in Signal Processing, Vol. 9, Hindawi Publishing Corp, 9 August 2007.
  • J. McAllister and R. Woods, Overview of a Compiler for rapid implementation and exploration of DSP systems on FPGA-based heterogeneous embedded platforms(invited paper), Special issue on Samos04, Journal of VLSI Signal Processing, Springer, Vol. 43, No. 2-3, June 2006, pp207 - 221.
  • Ying Yi and Woods, R., Hierarchical synthesis of complex DSP functions using IRIS, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 5, pp. 806-820, May 2005.
  • S. Govan, M. McLoone, C. Paar, and R. Woods, Guest Editorial: Cryptography algorithms and architectures for System-on-Chip, IEE Proc. On Information Security, Volume 1, Issue 1, p. 1-2, 2005.
  • Y.Yi, R.Woods, L.K.Ting, C.F.N.Cowan, High Speed FPGA-based implementations of Delayed-LMS filters(invited paper), Special issue on Sips02, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol. 39, Issue 1-2, Jan-Feb 2005, pp113-131.
  • L.K. Ting, R.F. Woods and C. F.N. Cowan, Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers, IEEE Trans. on VLSI Systems, Vol. 13, No. 1, Jan. 2005, pp86-95.
  • Lok-Kee Ting, Cowan, C.F.N., Woods, R.F., LMS coefficient filtering for Time-varying chirped signals, IEEE Trans. on Signal Processing, Vol. 52, Issue 11, Nov. 2004 pp. 3160-3169.
  • Turner, R.H., Woods, R.F., Highly efficient, limited range multipliers for LUT-based FPGA architectures, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 12, Issue 10, Oct. 2004, pp. 1113- 1118.
  • R. Woods, Clear future direction, IEE Review, Vol. 50, No. 6, pp56, Jun 2004.
  • R. Woods and R. Tessier, Guest Editorial: Field Programmable Logic, Journal of VLSI Signal Processing "Special Issue on Field Programmable Logic", Vol. 36, No. 1, pp5-6, 2004.
  • Lightbody, G, Woods, R. F. and Walke, R.L., Design of a parameterisable silicon intellectual property core for QR-based RLS filtering, IEEE Trans. on Very Large Scale Integration Systems, Vol. 11, No. 4, Aug 2003, 659- 678.